1. Field of the Disclosure
The present disclosure relates to the field of integrated circuits, and more particularly to the use of capacitors in signal processing applications.
2. Description of the Related Art
Capacitors are widely used in signal processing applications such as, for example, filtering, analog to digital converting, digital to analog converting, and the like. Often, multiple capacitors are used that need to have accurate capacitance values and/or ratios, for example, in switched capacitor circuits. Variations in semiconductor processing lead to capacitor mismatch, which can be a limiting factor in many circuits, for example, such as cyclic/pipelined analog to digital converters. The amount of capacitance that each of the multiple capacitors can vary from each other and have the circuit operate properly is referred to as a capacitor mismatch range and is based upon desired performance levels.
Smaller capacitors that meet the desired capacitor mismatch range are difficult to manufacture in semiconductor processes. A designer often increases the area of each capacitor, maintaining a similar ratio between the capacitors, to improve the manufacturability of the circuit. Increasing the area of multiple capacitors uses valuable circuit area, therefore increasing the cost of the integrated circuit. Additionally, increasing the area of a capacitor increases the load, therefore decreasing the power efficiency of the circuit. A tradeoff is often made between the size of the capacitors and the capacitor mismatch, affecting semiconductor yield.
A designer can also utilize multiple capacitors in parallel to reduce capacitor mismatch. For example, to achieve a 1:3 ratio, four similar sized or unit element capacitors can be used, one alone and three in parallel. Capacitors in parallel have less mismatch because the errors tend to cancel. Suppose two unit capacitors of nominal value, for example, 1 picoFarad (pF) are used to construct a 2 pF overall capacitive load. Let the mismatch of the capacitance be the ratio of the actual capacitance to the nominal or ideal capacitance. Assume the probability distribution of available capacitors is as shown:
Capacitance (pF)Probability of selectionMismatch0.9¼−10%1.0½   0%1.1¼+10%
Thus, the probability of plus or minus 10% mismatch is ¼+¼=½. Mismatch can be improved by combining two capacitors in parallel. The probability distribution for two such connected capacitors is
Capacitance Combination (pF)Probability of SelectionMismatch0.9 + 0.9¼ × ¼ = 1/16−10%0.9 + 1.0¼ × ½ = ⅛ −5%0.9 + 1.1¼ × ¼ = 1/16   0%1.0 + 0.9½ × ¼ = ⅛ −5%1.0 + 1.0½ × ½ = ¼   0%1.0 + 1.1½ × ¼ = ⅛ +5%1.1 + 0.9¼ × ¼ = 1/16   0%1.1 + 1.0¼ × ½ = ⅛ +5%1.1 + 1.1¼ × ¼ = 1/16+10%
With two capacitors, the probability of plus or minus 10% mismatch is 1/16+ 1/16=⅛, which is a reduction from using a single capacitor. However, two capacitors in parallel consume proportionately more power to drive the larger capacitive load.
Researchers have proposed active capacitor mismatch reduction utilizing additional analog processing per stage. However, more analog processing entails the use of larger capacitors to compensate for the added kT/C noise (and hence more load capacitance), and the need for additional clock phases in a clock cycle (and thus require more settling). Also, higher operational amplifier gains are required to reduce the added integrator leakage from increased analog processing.
Accordingly, it would be advantageous to have a technique for providing circuits with matched capacitances, without significantly increasing circuit area or load and improving semiconductor yield.
The use of the same reference symbols in different drawings indicates similar or identical items.